ISA - Instruction set architecture
Architecture - Memory layout, instruction set
Organization - implementation details (bus layout, processor implementation, etc)
architecture = API organization = code implementing the API
Quiz 1 prep
ISA
o-type (opcode) - halt i-type (immediate) - rx, ry, offset j-type (jalr) - Rx, Ry r-type: Rx, Ry, Rz
Other ISA features that aren’t in ours!!!
- can address by base + index
- instructions that aren’t the same length
- byte addressability (not fetching a 4-byte chunk at once)
Isa Construction
In a 32-bit byte addressable architecture, PC is incremented by 4 instead of 1 if an instruction is 4 bytes
this is to skip and not read part of an instruction in the IR
Calling Convention
T/F Local vars in a procedure are always allocated with registers
False. Can use memory and save in stack.
A frame pointer is needed because the stack pointer can change as addtl space is allocated. frame pointer provides a consistent reference
callee side saving registers
it does not know if everything has to be saved, so may be accessing memory unnecessarily
shadow register set
bad response
- inefficient use of resources
- expensive and takes time but not as much as memory so possibly saves time there?
good response
cannot do nested function calls, a register set will still be overwritten
Stack
Before callee finishes stack buildup
local variables <- stack pointer
saved $s registers (if planning to overwrite)
prev frame pointer <- callee starts, frame pointer
prev return address
addtl return values
addtl function params
saved t registers (if caller wants to keep)
Stack teardown
- Callee pops local vars, restores $s registers and frame pointer
- callee does JALR zero
- caller restores return address, stores return values if desired and pops return values and function calls - restores $t registers
When to save $s registers (what condition)?
clock cycle
processor runs at longest possible speed for a microstate
calc speed
datapath
1
Mem[MAR] → Reg[regno]$
2: new pop instruction setting and
DrReg, LdMAR, LdA, regsel=01 DrMEM, WrREG, regsel=00 DrALU, WrREG, func=11, regsel=01
Microcontroller
ROM vs Hardwired
Hardwired
Faster but expensive and harder to design
ROM
Flexibility for microcode Cheaper
3-ROM vs Single
3-ROM is slower