Topics To Review esp
- Trap Vector Table
- RET vs RTI
- Linking, compiling, assembling, preprocessing
Compilation
Preprocessing - change source code based on headers Linking - turn linked libraries etc into single source file Compiling - C into assembly Assembling - Assembly into machine code
RET vs RTI
RET is like JMP R7 RTI is RET but for traps or interrupt RTI stores on system stack and requires supervisor priviledge
I/O
Into R0
- can it be set to other registers? Polling - synchronous KBDR - keyboard data register, checks bit 15 for if input ready
- When KBSR is negative, stop polling
DDR vs DSR
DDR - holds character to display DSR - indicates if display is ready
Trap Table
starts at 0 Maps to handlers
Interrupt table
starts at 01 maps to handlers
INT signal only goes on when an interrupt is being serviced interrupts can only be serviced if it has a higher priority than current program
Processor Status Register (PSR)
- holds NZP in last 3 bits
- priveledge level in first bit
- Stores priority (3 bits, 0-7) Access Control Violation on attempting to access disallowed memory?? Priviledge = 0, then supervisor mode
Things to remember
RET = JMP R7 Trap table start
Write to display, read from keybaord