Goals
- Identify D flip flop, d latch, rs latch etc via circuit sim
- RS latch states (from table) and recording value
- address space vs addressability and computing
- Von neumman architecture
Logic
Sequential logic depends on past states Combinational logic is a result of direct inputs
Von Neumman Architecture
data and instructions stored in same
State Machine
S1: leftmost S0: rightmost bit
current state is S1S0 which is then moved depending on input immediate output is the output of input state
Edge vs Level
D-Flip-Flop - edge triggered, on rising edges Gated D Latch - high or low, level triggered
RS Latch
SR 1 1 steady state 1-0 reset state 0 0 - invalid
R stands for reset, so when R goes low, reset S stands for set, so when S goes 0, set value
Address
Addressability - bits stored in each location Address space - number of addresses (locations) or range
Calculating
e.g. (12 bit addresses), then spaces e.g. if 3 bit addresses, then spaces
- total memory = num spaces * num bits in each space (address space * addressability)
Registers and Memory
Register - d flip flops Memory - gated d latches
So registers are rising edge triggered and memory is level triggered
Control Signals
Are what come out of the FSM
- Control data flow and instruction execution
Fetch
performed every op, along with decode
Micros
Instructions
How to convert R6 to bits? (registers to bit) literally just 110 (numerical value in bits)
Condition Codes
anything with + sets condition codes LEA does NOT set CC
LD vs ST
LD loads from memory (read) ST stores into memory (write)
JMP vs BR
Control flow JMP is unconditional, BR can use nzp JMP is base register while BR is pcrelative
Offset and PCOffset range
What does PC* mean? Post-increment PC
Addressing modes
Ways to compute the address
PC Relative - ST, LD = mem[PC* + PCOffset9]
Indirect - STI, LDI = mem[mem[PC* + PCOffset9]]
Base Register offset - STR, LDr = mem[Base Regiser + offset6]
Differences:
PC Relative is limited by range Base Register can reach anywhere Indirect
STI vs STR
STORE (any store instruction)
- Load MAR with address
- Load MDR with data
- Store
STI is indirect addressing STR is base register + offset (I think) - 3 cycles
When to use a new clock cycle?
Need multiple items on the bus at the same time
IR and PC
PC holds next instruction address When does PC update? - After fetch What is the IR? holds value of current instruction
- How does it incorporate into ADD
Pseudo-op
.orig
starting address (inclusive)
Symbol Table
filled out first assembly pass just like label and addresses they map to
PC* is just the new PC offset
ADDR1MUX and ADDR2MUX
ADDR1MUX chooses between Base Register and PC for accessing memory ADDR2MUX chooses between offset (use PCOffset0 for pc relative and indirect, else offset6)
would use Base Register for LDR or STR
Extra Review
- STI, LEA, STR